ECEN 4623/5623 - Known Lab Issues and Current Status

  1. All Targets, Bad Parallel Port BIOS/CMOS Settings, CLOSED Issue, CMOS Should be set for PP address 0x3bc, IRQ 7, and Normal or SPP mode to work with standard VxWorks lptDrv.

  2. MMIO Regions for Bt878 and/or Cirrus 4281 PCI Cards

    Most targets have an MMIO region set up for PCI at 0x4000000, just above 64 MBytes of physical RAM. This works for targets in the lab which only have 32 or 64 MBytes of RAM. For home installs, you may want to increase this to 0x8000000 to sit above 128 MBytes of RAM or however much you have.

    Also, if you plan on using 2 Bt878 cards for stereo vision or 1 Bt878 + 1 Cirrus 4281 card for video conferencing, then you'll need to open up a second MMIO region. Opening this up at an offset of 0x1000000 to the first is a simple way to do this.

    To configure your BSP/Kernel for a new MMIO region you need to edit sysLib.c in your BSP directory. Edit the entries in the data structure sysPhysMemDesc and replace "DUMMY" entries with new MMIO regions as is shown below:

        /* SBS */
        /* entry for the Bt878 PCI MMIO  */
        {
        (void *) 0x04000000,
        (void *) 0x04000000,
        0x00001000, /* length */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
        },
        /* SBS */
    
        /* SBS */
        /* entry for the Bt878 PCI MMIO  */
        {
        (void *) 0x05000000,
        (void *) 0x05000000,
        0x00001000, /* length */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
        },
        /* SBS */
    

  3. All Targets, Bad PCI BIOS/CMOS Settings, CLOSED Issue, CMOS Should not be set for "PnP" Plug and Play - All PCI resources should be handled by VxWorks applications explicitly by programming the APIC OR the CMOS can be configured as follows to force BIOS to use one and only one IRQ routing on our boards:
    Make sure that settings are:
    
    1) PnP OS Installed: No
    2) Resources Controlled By: Manual
    3) Reset Configuration Data: Disabled
    
    4) That IRQs are as follows below
    
    IRQ0 - Legacy ISR (used by PIT)
    IRQ1 - Legacy ISR
    IRQ2 - Legacy ISR
    IRQ3 - Legacy ISR (programmed by Bt878 code and used for video)
    IRQ4 - Legacy ISR
    IRQ5 - Legacy ISR
    IRQ6 - Legacy ISR
    IRQ7 - Legacy ISR
    IRQ8 - Legacy ISR
    IRQ9 - Legacy ISR
    IRQ10 - Legacy ISR (USED by Etherlink III Network Interface Card)
    IRQ11 - Legacy ISR
    IRQ12 - Set this one to PCI/PnP ONLY - forcing BIOS to choose this IRQ alone (used for Cirrus 4281)
    IRQ13 - Legacy ISR
    IRQ14 - Legacy ISR
    IRQ15 - Legacy ISR
    
    Note: This issue showed up in a VoIP project, although I suspect this is an
    issue with Bt878 projects as well.  IRQ0 is the timer (typically 1 msec) and
    IRQ10 is the Etherlink III network card and it was easy to see that no
    interrupt was showing up in Windview when the VoIP did not work, but that
    IRQ12 (the intended IRQ) did show up when the VoIP project did work.
    
    As a lab convention, please always use IRQ 3 for the Bt878 and IRQ 12 for the Cirrus 4281.  If you do stereo vision with Bt878, then share IRQ 3 and determine the interrupting card by reading the status registers of both.  The 4281 and Bt878 can be used together, each with their own interrupt.
    
    Please do not change the CMOS setup without talking to me or the TA.  Thanks!
    

  4. ADC Board from Electronic Energy Control, Seemingly Random ADC Ouputs (not explainable by floating mux issue), OPEN Issue, group plans to call EEC and/or use substitute Weeder board.

  5. ADC Board from Electronic Energy Control, Bad ADC Channel Values, OPEN Issue, ADC Board will be replaced if it can't pass a diagnostic - Here's the diagnostic:
    Provide known reference pattern of 5v and Gnd inputs to each channel and verify:
    
    Mix     All 5v  All Gnd
    ---     ------  -------
    00      FF      00
    FF      FF      00
    00      FF      00
    00      FF      00
    FF      FF      00
    FF      FF      00
    FF      FF      00
    FF      FF      00
    
    Make sure you have Gnd and 5v ref for board and if the patterns can't be verified,
    then the ADC board is likely bad.
    

  6. ADC Board from Electronic Energy Control, Floating ADC Channels, CLOSED Issue, Here's a work around for this known problem:
    What I did was to tie unused channels high/low to create a start of frame
    and end of frame.
    
    E.g.
    
    Ch0 FF (5v)
    Ch1 00 (gnd)
    Ch2 XX (data)
    Ch3 XX (data)
    Ch4 XX (data)
    Ch5 XX (data)
    Ch6 XX (data)
    Ch7 00 (EOF)
    
    Since you can wrap to any starting point, you can see:
    
    Ch0 FF 00 XX XX XX XX XX 00 FF
    Ch1 00 FF 00 XX XX XX XX XX 00
    Ch2 XX 00 FF 00 XX XX XX XX XX
    Ch3 XX XX 00 FF 00 XX XX XX XX
    Ch4 XX XX XX 00 FF 00 XX XX XX
    Ch5 XX XX XX XX 00 FF 00 XX XX
    Ch6 XX XX XX XX XX 00 FF 00 XX
    Ch7 00 XX XX XX XX XX 00 FF 00
    
    I assumed this could float around on every frame, so I wrote a function to
    finde SOF and EOF on ever single set of 8 reads that I did.
    
    I did not see it change within one read of 8 values, but did throw out any
    data where I did not see valid SOF and EOF.
    
    So, just scan through all 8 looking first for FF 00 and when you find it,
    expect 00 five XX samples later -- read all 8 into a buffer first to build
    this frame.  Assume first sample after FF 00 (SOF) is lowest channel (Ch2) and
    one right before 00 EOF is Ch6.