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Li Shang
Assistant Professor
Ph.D. Princeton University 2004
Dissertation "System-level Power Analysis and
Optimization"
Research Interests
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High-performance Computer architecture
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Mobile
Computing
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Design for
Nanotechnologies
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Power/thermal analysis and optimization
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Embedded system design and synthesis
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Computer-aided design
Graduate Students
- Nicholas Allec
- Assem Bsoul
- Arlen Cox
- Kun Li
- Zyad Mohamed
- Yonghong Yang
- Changyun Zhu
Professional
Activities
Project Release
Publications
(Google scholar
citations)
2007
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[ICCAD] P. Zhou, Y. Ma, Z. Li, R. P. Dick, L. Shang,
H. Zhou, X. Hong, and Q. Zhou,
"3D-STAF: Scalable temperature and leakage aware floorplanning for
three-dimensional integrated circuits," in Proc. IEEE/ACM International
Conference on Computer-Aided Design
, Nov. 2007.
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[CODES-ISSS] C. Zhu, Z. Gu, R. Dick, and L. Shang,
"Reliable multiprocessor system-on-chip synthesis,," Proc.
International Conference Hardware/Software Codesign and System Synthesis, Sep. 2007.
(pdf)
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[CODES-ISSS] S. Chong, L. Shang, and R. P. Dick,
"Three-dimensional multi-processor system-on-chip thermal optimization,"
Proc.
International Conference Hardware/Software Codesign and System Synthesis, Sep. 2007.
(pdf)
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[TVLSI] Z. Gu, C. Zhu, R. Dick, and L. Shang,
"Application-specific MPSoC reliability optimization," IEEE Transactions on Very Large Scale Integration Systems
, to appear.
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[TCAD] A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha,
"System-level dynamic thermal management for high performance microprocessors," IEEE Transactions on Computer-Aided Design
, to appear.
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[MICRO] D. Brooks, R. Dick, R. Joseph, and L. Shang,
"Power, thermal, and reliability modeling in nanometer-scale microprocessors, " IEEE Micro
, 2007.
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[DAC] C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Knobel,
"Towards an ultra-low-power architecture using single-electron tunneling transistors, " in Proc. IEEE Design
Automation Conference, Jun. 2007. (Nominated for Best Paper Award) .
(pdf)
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[DAC] W. Zhang, L. Shang, and N. K. Jha,
"NanoMap: An integrated design optimization flow for a hybrid Nanotube/CMOS dynamically reconfigurable architecture, "
in Proc. IEEE Design Automation Conference, Jun. 2007 .
(pdf)
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[TCAD] L. Shang, R. P. Dick, and N. K. Jha,
"SLOPES: Hardware-software co-synthesis of low power real-time distributed
embedded systems with dynamically reconfigurable FPGAs",
IEEE Transactions on Computer-Aided Design, Mar. 2007.
(pdf)
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[DATE] Y. Liu, R. P. Dick, L. Shang, and H. Yang,
"Accurate temperature-dependent integrated circuit leakage power estimation is Easy, "
in Proc. IEEE Conf. on Design, Automation, and Test in Europe, Mar. 2007.
(pdf)
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[ISQED] Y. Liu, H. Yang, R. P. Dick, H. Wang, and L. Shang,
"Thermal vs. energy optimization for DVFS-enabled processors in embedded systems,"
in Proc. IEEE Proc. Int. Symp. Quality Electronic Design, Jan. 2007.
(pdf)
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[TCAD] Y. Yang, Z. P. Gu, C. Zhu, R. P. Dick, and L.
Shang, "ISAC: Integrated Space and Time Adaptive Chip-Package Thermal
Analysis," IEEE Transactions Computer-Aided Design, Jan. 2007.
(pdf)
2006
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[MICRO] N. Eisley, L.-S. Peh, and L. Shang,
"In-network cache coherence ", in Proc. IEEE/ACM International
Symposium on Microarchitecture, Dec. 2006. (pdf)
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[ICCAD] Y. Yang, C. Zhu, Z. P. Gu, L. Shang, and R. P.
Dick, "Adaptive multi-domain thermal modeling and analysis for integrated
circuit synthesis and design", in Proc. IEEE/ACM International
Conference on Computer-aided Design, Nov. 2006. (pdf)
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[Potentials] L. Shang and R. P. Dick "Thermal Crisis:
Challenges and Potental Solutions", IEEE Potentials,
Sept./Oct. 2006 (pdf)
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[DAC] W. Zhang, N. K. Jha, and L. Shang,
"NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture",
in Proc. IEEE Design Automation Conference, Jul. 2006. (pdf)
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[DAC] A. Kumar, L. Shang, L.-S. Peh, N. K.
Jha, "HybDTM: A Coordinated Hardware-Software Approach for Dynamic Thermal
Management", in Proc. IEEE Design Automation Conference,
Jul. 2006. (pdf)
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R. P. Dick, L. Shang, and N. K. Jha, "Power-Aware
Architectural Synthesis", to appear in The VLSI Handbook, 2006.
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[TCCA] N. Eisley,
L.-S. Peh, and L.
Shang, "In-network cache
coherence",
IEEE Computer Architecture Letters, vol 5,
no. 1, 2006. (pdf)
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[DATE] Y. Yang, Z. P. Gu, C. Zhu, L. Shang, and R. P. Dick,
"Adaptive chip-package thermal analysis for synthesis and design," in
Proc. IEEE Conf. on Design, Automation, and Test in Europe , Mar. 2006.
(pdf)
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[MICRO TOP PICK] L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha,
"Temperature-aware on-chip networks," IEEE Micro: Micro's Top Picks from
Computer Architecture Conferences (IEEE Micro - top pick),
Jan.-Feb. 2006. (pdf)
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[ASPDAC] Z. P. Gu, Y. Yang, J. Wang, R. P. Dick, and L. Shang,
"TAPHS: Thermal-aware unified physical-level and high-level synthesis," in
Proc. IEEE Asia & South Pacific Design Automation Conf. ,
Jan. 2006. (Nominated
for Best Paper Award) (pdf)
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[TCAD] L. Shang, L.-S. Peh, and N. K. Jha, "PowerHerd: A
distributed scheme for dynamic satisfying peak power constraints in
interconnection networks," IEEE Transactions on Computer-Aided Design,
Jan. 2006. (pdf)
2005
2004
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[TMC] L. Shang, R. P. Dick and N. K. Jha, "DESP:
A distributed economics-based subcontracting protocol for computation
distribution in power-aware mobile ad-hoc networks," IEEE
Transactions on Mobile Computing, vol. 3, no. 1, Jan. 2004, pp. 33-45.
(pdf)
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[MICRO] L. Shang, L.-S. Peh, A Kumar and N. K. Jha, "Thermal
modeling, characterization and management of on-chip networks,"
in Proc. IEEE/ACM International Symposium on Microarchitecture , Dec 2004. (pdf)
2003
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[ICS] L. Shang, L.-S. Peh and N. K. Jha, "PowerHerd:
Dynamic satisfaction of peak power constraints in interconnection networks,"
in Proc. ACM International Conference on Supercomputing, pp
98-108, June 2003. (pdf)
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[GLVLSI] W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S.
Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, "A
comprehensive high-level synthesis system for control-flow intensive
behaviors," in Proc. ACM Great Lakes VLSI Symposium ,
pp. 11-14, Mar. 2003. (pdf)
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[HPCA] L. Shang, L.-S. Peh and N. K. Jha, "Dynamic
voltage scaling with links for power optimization of interconnection
networks," in Proc. IEEE International Symposium on
High-Performance Computer Architecture, pp. 79-90, Jan. 2003. (pdf)
2002
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[PDCS] L. Shang, R. P. Dick, and N. K. Jha, "An
economics-based power-aware protocol for computation distribution in
mobile ad-hoc networks," in Proc. IASTED International
Conference on Parallel and Distributed Computing and Systems,
pp. 344-349, Nov. 2002. (Best Paper Award) (pdf)
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[TCCA] L. Shang, L.-S. Peh and N. K. Jha, "Power-Efficient
Interconnection Networks: Dynamic Voltage Scaling with Links,"
Computer Architecture Letters, vol 1,
no. 2, May 2002, pp. 1-4. (pdf)
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[FPGA] L. Shang, A. S. Kaviani, and K. Bathala "Dynamic
power consumption in VirtexTM-II FPGA," in Proc. ACM
International Symposium on Field-Programmable Gate Arrays ,
pp.157-164, Feb. 2002. (pdf)
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[VLSI] L. Shang, and N. K. Jha "Hardware-software
co-synthesis of low power real-time distributed embedded systems with
dynamically reconfigurable FPGAs," in Proc. IEEE
International Conference on VLSI Design, pp. 345-352, Jan.
2002. (pdf)
2001
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[ICCD] L. Shang, and N. K. Jha "High-level
power modeling of CPLDs and FPGAs," in Proc. IEEE
International Conference on Computer Design, pp. 46-51, Sep.
2001. (pdf)
2000
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L. Shang, Y.-Q. Ge, and R.-D. Zhou, "Embedded
microprocessor IP design and analysis," Microelectronics, vol.
30, no. 1, Jan. 2000, pp. 28-30.
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Contact Info.
Engineering Center, OT358
University of Colorado at Boulder
425 UCB
Boulder, CO 80305
Phone:
(303) 492-8785
Email
li.shang<at>colorado<dot>edu
Teaching
874 High-performance on-chip systems
451 Digital integrated circuit engineering
ECEN 2120 Computers as components
426 Real-time systems
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