Fall 2008 Syllabus -- Academic Calendar, ECE Resources
Please See CULearn.colorado.edu and log into ECEN5623/4623 online for more course info and Lab Assignments!!
08/25 Class: Introduction - Lecture 1 , PDF Download
- Course goals
- Course project
- Course grading (see policy below)
- Video Tape: Project from Previous Semesters (Robotics, Video, Audio)
- RT Embedded System TERMINOLOGY
INITIAL QUIZ REVIEW - Terminology Overview
Wikipedia (Great Resource for Technical Terminology)
Hands on lab night #1 - Tornado/VxWorks lab introduction (code build, load, and logistics)
- Brief VxWorks Demo - Programmer's Guide - Chapter 2, Basic OS
- Tornado host development system
- WDB target server
- "launch" tool target manager
- Windshell
- Windview - "Software Logic Analyzer"
- Browser
Read: RTECS (Real-Time Embedded Components and Systems) - Chapter 1
09/01 Class: NO CLASS - LABOR DAY HOLIDAY
09/08 Class: Fundamentals of Real-Time Theory - Lecture 2, PDF Download
- What's makes distributed, real-time, embedded multitasking systems challenging?
- Best effort, Hard real-time, Soft real-time
- Scheduling Class Taxonomy
- Best Effort scheduling (Round-Robin Timeslice Scheme - Review)
- Intro to Fixed priority preemptive scheduling
- Intro to Dynamic priority scheduling
- Utility Curves
Paper: Liu and Layland Rate Monotonic paper
Read: RTECS - Chapter 2
PROJECT BACKGROUNDER: ROBOTICS, Lecture-Robotics, PDF Download
09/10 Project Proposal DUE
09/12 Lab-0 DUE
09/15 Class: Fundamentals of RT Theory Cont'd - Services and High-Level Design - QUIZ on Terminology Overview, Lecture 3 , PDF Download
INITIAL QUIZ - On Terminology
Real-Time Services
- What a Service Release Timeline Really Looks Like
- The CPU, I/O, Memory Resource Space (Characterizing RT Applications)
- Intro to Timing diagrams (interference)
- Intro to Hard real-time safe resource utilization bounds
Case study #1: High-Level RT System Design Examples
PROJECT BACKGROUNDER: DESIGN METHODS, Lecture-Design, PDF Download
EXAMPLE - Space Infrared Telescope Facility Instrument Control (launched on August 25, 2003)
- The hard real-time requirements and performance
- What worked, what didn't and why
- Overview Presentation
- The Test Image
EXAMPLE - DATA-CHASER, Space Shuttle Hitch-hiker Class Payload Flown on STS-85, Summer 1997, DATA-CHASER HTML
Paper: Audsley DM paper
09/22 Class: RM/DM Policy and Feasibility Test Derivation - Lecture 4 , PDF Download
Rate Monotonic Policy and Feasibility Overview
- Rate Monotonic Assumptions and Constraints
- More on Fixed priority preemptive scheduling
- Overview of Derivation of RM LUB - Hard real-time safe resource utilization bounds
- More on Dynamic priority scheduling (Earliest Deadline First and Least Laxity First)
- EDF and LLF Overview
Introduction to Feasibility Tests
- Sufficient Tests - RM LUB, DM
- N&S Tests
- Scheduling Point
- Completion Test
Deadline Monotonic Policy and Feasibility Overview
- DM Sufficient Feasibility Test
- DM Sufficient and More Necessary Test
Beyond RM and DM:
- Scheduling Point Feasibility Test
- Completion Test Feasibility Test
- Sufficient vs. Necessary and Sufficient Feasibility Tests
- Computational Complexity of Feasibility Tests (O(1), O(n^2), O(n^3))
RMA Analysis Tool Vendors - RapidRMA, TimeSys
PROJECT BACKGROUNDER: COMPUTER VISION, Lecture-Computer-Vision, PDF Download
Read: RTECS - Chapter 3
Hands on lab night #2 (code build, load, and signle step debug)
- VxWorks TCB (Task Control Block)
(Read/Browse POSIX section of VxWorks Ref. Man. 5.4)
- VxWorks example code demo
- Using GDB to debug a task or the system
09/24 Project High Level Design DUE
09/26 Lab-1 DUE
09/29 Class: RM Implementation Challenges: Services, Synchronization and Shared Resources - Lecture 5 , PDF Download
Paper: Priority Inheritance Protocols
"Priority inheritance protocols: an approach to real-time synchronization", Sha, L.; Rajkumar, R.; Lehoczky, J.P.; Computers, IEEE Transactionson, Volume: 39 Issue: 9, Sep 1990.
Paper Available on:IEEE Publications Page
HW and HW+FW Implementations of RT Services
- ISRs, task canonical structure, and task/service release
- FPGA/ASIC-based State Machines for Offloading
- Microprocessor/Microcontroller Offloading
- DSP Offloading
SW Implementations of RT Services
- Main+ISR Executive
- Cooperative Non-Preemptive Threads
- Callbacks
- Continuation Functions
- Software State-Machines
- Priority Preemptive Run-to-Completion RTOS
- Time-sliced Traditional Best Effort OS
Synchronization and Resource Issues:
- Problems with Blocking (resources other than CPU, e.g. I/O)
- Break up into more threads (better scheduling control)
- Interrupt driven I/O - e.g. Programmable FIFOs
- Model Blocking Time
- Priority inversion (general concept)
- Unbounded priority inversion problem (mutex C.S.)
- Priority inheritence
- Priority ceiling
Other Practical Problems - Solutions:
1) Estimating C (execution jitter) - use WCET
2) Period jitter - transform to highest frequency
3) ISR and context switch overhead - add to WCET
4) Deadlock/Livelock - HW Watch Dog
5) Bad code spinning and wedging - Sanity Monitoring
Case Study #2: Mars Pathfinder (As presented from multiple perspectives)
Mike Jones Overview or What Happened to Mars Pathfinder
Mars Pathfinder -- WRS Story
Mars Pathfinder -- JPL Story
PROJECT BACKGROUNDER: CONTINUOUS MEDIA (VOIP/VIDEO), Lecture-Media, PDF Download
Read: RTECS -- Chapter 4 & 5
10/06 Class: Real-Time Service System Integration and IO
(Post Release Service IO and VxWorks Inter-Task Communication) - Lecture 6 , PDF Download
Service Synchronization, Communication, and IO
- Using Message Queues to Sync Services and for Communication
- Using Binary Semaphores to Sync Services
- What about IO during Service Execution?
Overlapping CPU and IO Cycles - Latency Hiding
- Initial Release Input - Block DMA and FIFO Sensor Data
- Intermediate IO
- Memory-Mapped IO During Service Processing
- Hiding IO latency with Overlap
System Design with RT Services
- Software process: analysis, design, specification, coding,
unit testing, integration, system testing,
delivery, operations
- Implementation characteristics: tasks, message passing,
synchronization, ISRs,
memory-mapped I/O, bus
interface, signals, shared
memory, stack/data/heap
mgt., comm. interfaces
- Specifying the design of real-time software systems
Data flow and Control flow (function and interfaces)
Extended finite state machines and signal block diagrams
MSC (multi-tasking multi-node protocol/comm model)
Hands on lab night #3 (code build, load, and logistics)
- Processes, threads, and tasks, what's the diff?
- VxWorks TCB (Task Control Block)
(Read/Browse POSIX section of VxWorks Ref. Man. 5.4)
- VxWorks switch hook demo
- VxWorks Services
Read: RTECS - Chapter 6
10/08 Project Detailed Design DUE
10/10 Lab-2 DUE
10/13 Class: Scalable Embedded Systems Architectures Lecture 7 , PDF Download
Intro to PCI Architecture and I/O Architectures
- Intro to PCI bus architecture and device interfaces
- Comparison of PCI with older VME Bus
VME Word and block transfer vs. PCI Burst
VME Asynch address and data modes vs. PCI Sync A/D 32/64 and Config Space
- PCI Plug and Play Concept
- Embedded System PCI Form Factors and Standards
CompactPCI, PC/104+ (PCI+ISA), PMC, PCI-X 1.0a/b, PCI-X 2.0, PCI-Express
Read: Shanley Text, (chapters 1*, 2*, 5, and 6) *=required, others suggested
- Discussion on I/O Trends (High speed differential serial)
USB
PCI-Express
10G Ethernet (10GEA), which became IEEE P802.3ae
RapidIO
Other High-speed Serial: Firewire, RapidIO, SAS/SATA
- Discussion of ASIC Trends
SoC (Yesterday's Board, Today's Chipset, Tomorrow's ASIC)
Core + I/O (PowerPC 8xx, 82xx)
Reconfigurable (Virtex II)
Configurable (Tensilica)
IP Modules (CPU Cores, Mem Ctlrs., Local Bus)
Off-loading (Today's SW is tomorrow's HW)
Hands on lab night #4 (code build, load, and logistics)
- The POSIX 1003.1b compliant Embedded system environment (VxWorks)
- The POSIX Application Programmer's Interface
- POSIX overview: message queues, RT signals, and semaphores
- Clocks and timers
10/20 Class: Device Drivers and Characterization of Embedded I/O Lecture 8 , PDF Download
I/O interfaces
- Digital
- Analog (ADC, DAC interfaces)
Microprocessor interface types (word or block)
- Register-based control, status, data
- Higher rate FIFO I/O
- Block-oriented 1st/3rd party DMA tx/rx between I/O interfaces and memory
- Bus burst transfers and block transfers
- system memory map for MMIO devices - DRAM/SDRAM/DDR, BOOTROM, Flash
External interface types
- CPU local bus IO/MMIO
E.g. PCI 2.x, GPIO, DRAM, Flash
- Point-to-point or switched devices
E.g. RS-232, RS-422, PCI-Express
- Network multi-access devices
E.g. Ethernet
Device interfaces -- introduction to drivers
- top half (driver entry point interface to tasks)
- bottom half (interface to devices)
- ring buffers
- blocking/non-blocking
- ioctl "swiss army knife"
- ISRs and signals/semaphores
- scheduled I/O (handle buffering and processing in task)
Read: Shanley Text, (chapters 14*, 17*, 18*, 19*, 26, and 28) *=required, others suggested
Mid-term Review: Lecture MT-Review , PDF Download
10/24 Lab-3 DUE
10/27 Class: MIDTERM
MIDTERM (1.5 hours)
11/03 Class: Real-Time Performance, Measuring Performance and HW/SW Debugging Techniques Lecture 11 , PDF Download
MIDTERM solution overview/questions - exams returned
PowerPC Architecture:
PowerPC 8xx architecture review HTML
Power PC 8xx and 82xx Architecture Power Point Overviews
Xscale Architecture:
Xscale Architecture Docs
x86 Architecture:
IA32 Architecture Docs
Estimating/Measuring Performance Based on CPU Architecture
IBM Paper on Performance Monitoring and Tuning
- Measuring/Controlling CPU Efficiency
- Trace Ports (e.g. IBM PowerPC 4xx series, Strong Arm)
- Built-in PMU (Performance Monitoring Units) (e.g. Intel Pentium, Xscale)
- External Methods
- Logic Analyzer Memory Traces (Cache Misses, DMA, Un-cached access)
- Memory Port Markers (Writes to Un-cached Memory)
- Profiling Code by Function or Block
- Software in Circuit Methods (e.g. CodeTest Trace SW In-Circuit, gprof)
- Hardware Supported Profiling (e.g. Intel Vtune, CodeTest HW In-Circuit)
- Cycle-based profiling
- Event-based profiling
- Cache Coherency
- Harvard I-Cache, D-cache Architecture
- Cache Invalidate, Flush, Lock, Pre-fetch
- Measuring/Controlling I/O Efficiency
- Bus Analyzers - e.g. PCI Event Traces
- Logic Analyzer with Support Package
- PCI Bus Performance Tuning
- Bus Grant Arbiters and Priority Schemes, Minimum Burst Length
- PCI-Express Performance Features - PCI Express Tutorial
- Isochronal Virtual Channels
- Split Transaction
Hands on lab night #5 (boot, kernel, and JTAG debugging)
- IEEE 1149.1 JTAG Test Access Port and Boundary Scan Standard
- Using a JTAG for BSP Development (VxWorks)
- The VxWorks Bootrom Boot Loop and BSP
- Kernel configuration, build, and debugging
Paper: Zen of BDM
11/05 Project Test and Integration Plans DUE
11/10 Class: Embedded Volatile and Non-volatile Memory Devices Lecture 12 , PDF Download
Memory Technologies and Hierarchy
- Harvard Arch. I-Cache, D-Cache (Separate instruction and data cache)
- L1 On-Chip, L2/L3 Off-Chip Cache
- SRAM (Fast, but expensive per bit stored)
- DRAM, SDRAM, DDR (Double Data Rate DRAM), Quad Rate SRAM
ECC (Error Correcting Circuitry) memory
- Hardware/Software Design
- Hamming encoding for EDAC (Error Detection and Correction) - review handout provided
- ECC and maintenance and handling of SBEs and MBEs
- Firmware ECC Req'ts:
1) initialize memory fully,
2) handle SBE interrupts, MBE check-stop, and
3) background scrubbing
Non-Volatile Memory Devices and Systems
- EPROM, EEPROM, NVRAM, and Flash (NAND, NOR, SFDC)
- Flash File Systems - TrueFFS
- Ferroelectric RAM technology - Overview
11/17 Class: High Availability vs. High Reliability (Same?)Lecture 13 , PDF Download
IBM developerWorks Paper on HA and HR
Definition of High Availability (5 9's)
- System is ready to provide service 99.999 % of any given service year
- System can crash, but must reboot with minimal interruption to services and returning to fully service availability quickly
Definition of High Reliability
- Formal methods and testing to prove reliability is designed in and built in
- SW Path coverage, statement coverage, and condition coverage criteria
- HW Simulation testing with SW drivers
- HW built-in test (Built-in Logic Analyzers, JTAG, Built-in Performance Monitoring Counters)
- System Safe Modes
Recovery Concepts
- Conservative Safe Mode Manual Recovery (typical of satellite systems)
- Automatic Recovery (typical of high availability sytems)
Final Review: Lecture Final-Quiz-Review , PDF Download
Case Study #3:RACE Hard and Soft Real-Time
- Is there a compromise between hard real-time and best effort?
- digital control and CM pipelines
- Video Tape: RACE Platform
11/24 Class: NO CLASS - FALL BREAK
12/01 PROJECT WRITE-UP due in my e-mail inbox or submitted to WebCT no later than midnight!!! (No late projects)
12/01 Class: LAB NIGHT
12/08 Class: LAB NIGHT, FINAL QUIZ
12/15 Class: FINAL DEMO NIGHT
11/17 - 12/15 - Project Debug or Demo Sessions (Scheduled by e-mail with Instructor)
12/19 - Grades Finalized