An in-depth study of compiler backend design for high-performance architectures. Topics include control-flow and data-flow analysis, classical optimization, instruction scheduling, and register allocation. Advanced topics include memory hierarchy management, optimization for instruction-level parallelism, modulo scheduling, predicated and speculative execution. The class focus is processor-specific compilation techniques, thus familiarity with both computer architecture and compilers is recommended.
Course Topics/Outline
- I. Analysis
- Control flow graph
- Data dependence
- Def-use chains, Dominator, reaching definition, available expression
- II. Representation
- SSA (Static Single Assignment)
- PDG (Program Dependence Graph)
- III. Traditional optimization
- Subexpression elimination, dead code
- IV. Interactions between architecture
- Register Allocation and Graph Coloring
- V. Profiling, instrumentation, and performance analysis
- Collection of application execution information
- Performance estimation (cache, branch prediction, code size)
- VI. Advanced optimization
- Loop unrolling
- Profile
- guided optimization (superblock)
- Schedliing
- VII. Advanced optimization II and advanced analysis
- Function inlining
- Interprocedural analysis
- VIII. Run-time Optimization
- Binary instruction and dynamic compilation